Referring now to FIG. 1, in a dynamic random access memory array having a folded bitline architecture, a plurality of rowlines, RL1-RL4, intersect a plurality of digit line pairs, DL1-DL2 and DL3-DL4. The intersection of each rowline and each digit line provides a memory cell location, and represents a uniquely addressable data bit. During a read operation, when the charge stored in a cell, MC1-MC8, is dumped to a one digit line of a digit line pair by activating the rowline associated with that cell, the other digit line of the digit line pair provides a reference voltage level. Each digit line pair has associated therewith both a P-channel sense amplifier that is responsible for pulling the digit line having the marginally higher voltage level up to a voltage level close to power supply voltage, and an N-channel sense amplifier that is responsible for pulling the digit line having the marginally lower voltage level down to a voltage level close to ground potential.
Since the maximum voltage that can be written to a DRAM cell (V.sub.M) is equal to the voltage applied to word lines V.sub.WL minus a threshold voltage (V.sub.t), V.sub.M is the optimum voltage level to which digit lines should be pulled up by the P-channel sense amplifiers. In the interest of longer refresh periods, lower soft error date, and more robust capability to distinguish between a stored "0" and a stored "1", it has been found useful to apply a voltage to the word lines that is greater than the power supply voltage V.sub.CC so that full power supply voltage can be written to a cell to represent a "1" value. U.S. Pat. Nos. 4,543,500 and 4,533,483, both of which issued to Joseph C. McAlexander, III, et al. described such a technique. In fact, the voltage applied to the word lines is typically considerably greater than a V.sub.t amount above V.sub.CC, as this permits much faster voltage transitions. This is due to the fact that current flow through the access transistor ramps down rapidly as the voltage on the digit line approaches a V.sub.t amount below the word line voltage.
referring once again to FIG. 1, the DRAM array depicted therein has non-bootstrapped word lines (i.e., V.sub.WL is equal to the power supply voltage) and a prior art pull-up circuit for P-channel sense amplifiers. For such an array, V.sub.M is, of course, equal to V.sub.CC -V.sub.t. It will be noted that each digit line pair DL1-DL2 and DL3-DL4 in this DRAM array is shared by two memory sub-arrays, SA1 and SA2, with each digit line pair having a single P-channel sense amplifier, PS1 and PS2, located at one end of the digit line pair, and a single N-channel sense amplifier, NS1 and NS2, located between the two sub-arrays. Each P-channel sense amplifier (PS1 and PS2) is coupled to the pull-up node P.sub.VT through a PMOS write transistor (PW1 and PW2, respectively). Each PMOS write transistor is controlled by signal WT. Each N-channel sense amplifier (NS1 and NS2), on the other hand, is coupled to ground through an NMOS coupling transistor, NC1 and NC2, which are controlled by signal NLAT.
Still referring to FIG. 1, each sub-array is isolatable from the N-channel sense amplifier by means of a natural NMOS isolation transistor in each digit line, ISO1-ISO8. Each digit line in a digit line pair is coupled to separate input/output lines, IO1-IO2. The input/output lines IO1 and IO2 are coupled to multiplexers MUX1 and MUX2, respectively. By having two sub-arrays share a digit line pair, and by activating only one pair of isolation devices so that only the sub-array being addressed is coupled to the N-channel sense amplifier during sensing operations performed by the N-channel amplifier, digit line capacitance may be effectively halved. Once an N-channel sense amplifier has begun to pull one of its associated digit lines to ground potential, the remaining pair of isolation devices is activated in order to (in the case of the lower array) couple the digit lines to the P-channel sense amplifier, and (in the case of the upper array) couple the digit lines to the N-channel column decode transistors DQ1-DQ4. The column decode transistors are activated by a column decoder, CD, which is coupled to the address bus AB.
Still referring to FIG. 1, it will be further noted that a natural NMOS transistor QNA is placed between a PMOS active pull-up transistor QP and the pull-up node P.sub.VT. The NMOS transistor QNA limits the pull-up voltage on node P.sub.VT to V.sub.CC minus the V.sub.1 of the NMOS transistor QNA, which is approximately 0.6 volt. Were it not for the NMOS transistor QNA, the P.sub.VT node would be pulled up to a full V.sub.CC, as would be the digit lines within the upper sub-array SA1. However, since the NMOS sense amplifier isolation transistor between the two sub-arrays ISO1-ISO4 would drop this voltage to V.sub.CC minus 0.6 volt, performance of the upper and lower sub-arrays would not be well balanced. NMOS cell access transistor ISO1-ISO8 typically have a V.sub.t of about 1.0 volt, and although it would be ideal, in once sense, to have the same V.sub.t drop in the pull-up circuit, the use of an NMOS transistor having a V.sub.t of 1.0 volt would increase pull-up times significantly. Thus, the use of the NMOS transistor QNA in the pull-up circuit is a compromise between the need for speed and the need to achieve operational voltage balance.
Most significantly, the architecture of FIG. 1 is characterized by slow pull-up times, particularly for the portions of the digit lines within the lower sub-array SA2. FIG. 2 graphically represents the pull-up voltages as a function of time. Plot A represents the voltage on the P.sub.VT node; plot B represents the voltage on portions of the digit lines within the upper sub-array SA1; and plot C represents the voltage on portions of the digit lines within the lower sub-array SA2.
What is needed is a new pull-up circuit for P-channel sense amplifiers, in a DRAM array having unbooted word lines, that will decrease the time required to pull up the voltage on all portions o the digit lines to V.sub.M.